1. Field of the Invention
The present invention relates to a method for forming an isolation layer of a semiconductor device, and more particularly to a method for preventing the deterioration of a leakage characteristic due to the formation of a liner nitride layer in a peripheral circuit region.
2. Description of the Prior Art
In order to increase data retention time, which is retention time of data stored in a DRAM cell, that is, **to improve refresh characteristic, technology has been introduced, which forms a liner nitride layer before the deposition of an oxide layer buried in a trench in a shallow trench isolation (hereinafter, referred to as an STI) process.
Herein, the improvement in the refresh characteristic is resulted from stress alleviation and diffusion prevention on an isolation layer by the liner nitride layer.
Further, the formation of the liner nitride layer may be preferred in a cell region, but it causes a leakage in an off state, which is called hot electron induced punchthrough (HEIP), in a P+ well region of a peripheral circuit region. Such a phenomenon is disclosed in a document entitled “Ref. S. J. Ahn, et. al., IEEE 40th annual international reliability physics sympo, 2002, p 365–368”.
According to that document, the hot electron induced punchthrough frequently occurs in a transistor to which a high voltage is applied. Especially, since a pMOS uses a buried channel, the hot electron induced punchthrough more frequently occurs in a PMOS than an nMOS.
FIG. 1 is a sectional view illustrating a leakage characteristic due to the formation of a liner nitride layer on a cell region and a peripheral circuit region according to the prior art.
As shown in FIG. 1, since an N− well 2a is formed in the cell region, electron trapping due to the liner nitride layer 5 does not occur. Accordingly, the deterioration of a leakage characteristic due to the formation of the liner nitride layer 5 does not occur.
In contrast, the electron trapping due to the liner nitride layer 5 occurs in a P+ well region 2b in the peripheral circuit region, so that attractive force acts on holes on an interface between substrate active silicon and a sidewall oxide layer 4 and an interface between the sidewall oxide layer 4 and the liner nitride layer 5. Therefore, a leakage characteristic deteriorates.
As described above, the liner nitride layer is formed to improve refresh characteristic in a DRAM device and actually improves the refresh characteristic in the cell region, thereby improving the properties of a device. However, the liner nitride layer deteriorates the leakage characteristic in the P+ well region of the peripheral circuit region. Accordingly, it is necessary to prevent the leakage characteristic from deteriorating in the peripheral circuit region.